For a hardware (HW) of a network interface card (NIC), a device that is provided with a network congestion control function have emerged in recent years for the purposes of offloading a load of a CPU (Central Processing Unit) and controlling sending and receiving of data with a high degree of accuracy. The NIC provided with above function is capable of compensating for reduction in CPU performance associated with power saving in the device and controlling sending and receiving of data with a high degree of accuracy in a broadband and low-delay local area network (LAN) such as a data center.
The NICs provide functions such as end-to-end congestion control for each flow and rate shaping. The functions have been originally performed in a software stack (mainly in the Transmission Control Protocol/Internet Protocol (TCP/IP) layer) of an operating system (OS), as hardware functions.
FIGS. 16, 17 and 18 are block diagrams illustrating configurations of a communication system, a terminal, and an NIC provided in the terminal according to a related art. Referring to FIG. 16, the communication system includes terminals 101-1 to 101-N and a network 2. In the following description, suffixes on reference numerals of each circuitry and software, such as “-1” to “-N” and “-1” to “-(N−1),” will sometimes be omitted.
Referring to FIG. 17, a terminal 101 includes, as software (SW) components, an application 4 for sending and receiving data and a device driver 6 for causing a device to operate. In addition, the terminal 101 includes, as hardware (HW) components, a CPU 7, a memory 8, a root complex 9, and an NIC 105 for sending and receiving data.
Referring to FIG. 4, the device driver 6 includes a memory region (MEM region) 10 and a direct memory access control (DMACTL) unit 11. The MEM region 10 holds data coming from the application 4 in association with each destination identifier (ID). The DMACTL unit 11 controls a DMA unit 112 in the NIC 105.
Referring to FIG. 18, the NIC 105 includes a direct memory access (DMA) unit 112, rate control units 114-1 to 114-(N−1), and a network interface (NW I/F) 115. The DMA unit 112 retrieves required data from the memory 8 of the terminal 101. Each of the rate control units 114-1 to 114-(N−1) controls a sending rate at which data destined for each destination ID are sent out to the network. The network interface 115 is an interface for connecting to the network 2. Each rate control unit 114 includes a buffer 117 for holding data until a data transmission opportunity arises and a rate control timer 118 which controls data transmission opportunities.
The communication system according to the related art that has the configuration described above operates as follows.
The application 4 in the terminal 101 sends data to be sent to each destination ID to the device driver 6. Then, the device driver 6 saves the received data in the memory region 10 in association with each destination ID.
When any of the buffers 117-1 to 117-(N−1) (for example, the buffer 117-1) in the rate control units 114-1 to 114-(N−1) is freed, the DMA unit 112 in the NIC 105 issues a DMA request to the memory region 10 of a destination ID corresponding to the buffer 117-1 among the memory regions 10 in the device driver 6. The device driver 6 sends data in the memory region 10 associated with the destination ID to the requested buffer 117-1 in response to a completion responding to the DMA request.
Further, when any of the rate control timers 118-1 to 118-(N−1) in the rate control units 114-1 to 114-(N−1) is expired, the rate control timer extracts data from the buffers 117-1 to 117-(N−1) connected to the rate control timer and sends the data to the network 2 through the NW I/F 115. Then, the rate control timers 118-1 to 118-(N−1) in the rate control units 114-1 to 114-(N−1) activate rate control timers on the basis of a sending rate set therein.
In this way, the NIC 105 which provides a rate control function as hardware can perform rate control for each destination terminal by including the buffer 117 and the rate control timer 118 inside for each destination ID. This enables control with a higher degree of accuracy than control performed by the CPU 7 while reducing a load on the CPU 7.
HW that has the function as described above is disclosed in PTL 1 and PTL 2, for example. PTL 1 describes a technique of holding data destined for each destination ID in the same First-In First-Out (FIFO) queue with the aim of simplifying a configuration, and then sending out the data to a network. PTL 2 describes a technique of holding data destined for destination IDs in the respective FIFO queues and further controlling a rate control timer associated with each of classes categorized into different destination IDs.